# For complete documentation of this file, please see Geany's main documentation
[styling=Verilog]

[keywords]
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word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof break buf bufif0 bufif1 case casex casez cell checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endsequence endspecify endtable endtask enum eventually expect export extends extern final first_match for force foreach forever fork forkjoin function generate global if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inside instance interface intersect join join_any join_none let liblist library local macromodule matches modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or package packed pmos posedge primitive priority program property protected pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with sequence showcancelled soft solve specify static strong struct super sync_accept_on sync_reject_on table tagged task this throughout timeprecision timeunit tran tranif0 tranif1 typedef union unique unique0 until until_with untyped use virtual wait wait_order weak while wildcard with within xnor xor
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word3=bit byte chandle event genvar highz0 highz1 inout input int integer interconnect large localparam logic longint medium output parameter pull0 pull1 real realtime ref reg scalared shortint shortreal signed small specparam string strong0 strong1 supply0 supply1 time tri tri0 tri1 triand trior trireg type unsigned uwire var vectored void wand weak0 weak1 wire wor
docComment=

[settings]
lexer_filetype=Verilog
tag_parser=SystemVerilog

# default extension used when saving files
extension=sv

# MIME type
mime_type=text/x-systemverilog

# these characters define word boundaries when making selections and searching
# using word matching options
#wordchars=_$abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789

# single comments, like # in this file
comment_single=//
# multiline comments
comment_open=/*
comment_close=*/

# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
# 		#command_example();
# setting to false would generate this
# #		command_example();
# This setting works only for single line comments
comment_use_indent=true

# context action command (please see Geany's main documentation for details)
context_action_cmd=

[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
